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HRD Corp Approved Training Provider Malaysia - Industrial 4.0 Certification Training and Education

Verilog Programming Training for FPGA

A meticulously crafted Verilog Programming Training for FPGA enthusiasts and professionals, positioning them at the forefront of modern logic design. Participants will gain a profound understanding of VERILOG syntax and the pivotal coding styles that resonate with efficient logic design. The training emphasizes writing VERILOG RTL hardware designs with a keen focus on best coding practices, ensuring robust and optimized outcomes.

Navigating deeper, learners will be enlightened on the synthesizable subset of VERILOG, coupled with the know-how of addressing problematic coding issues in hardware. The course curriculum further integrates essential skills like printing messages in testbenches and scripting transaction-based testbenches using subprograms. With hands-on guidance on leveraging VERILOG simulation and synthesis tools, participants will be fully equipped to pioneer innovative FPGA solutions and drive excellence in their respective domains.

Certificate

All participants will receive a Certificate of Completion from Tertiary Courses after achieved at least 75% attendance.

Funding and Grant

HRD Corp Claimable Course for Employers Registered with HRD Corp

HRDF claimable

Course Code: M423

Course Booking

MYR2,000.00

Course Date

Course Time

* Required Fields

Post-Course Support

We provide free consultation related to the subject matter after the course. Please email your queries to sales@tertiarycourses.com.my and we will forward your queries to the subject matter experts and get back to you asap.

Course Cancellation/Reschedule Policy

We reserve the right to cancel or re-schedule the course due to unforeseen circumstances. If the course is cancelled, we will refund 100% to participants.
Note the venue of the training is subject to changes due to class size and availability of the classroom.
Note the minimal class size to start a class is 3 Pax.


Course Details

Day 1

FPGA Design FLOW

  • Motivation

Topic 1 : Architecture of FPGA

  • Introduction to Programmable logic device (PLD)
  • Architecture
  • Structure of PLD

Topic 2 : Introduction to Verilog

  • Levels of Abstraction
  • Syntax & Semantics
  • Reserved Keywords

Topic 3: Verilog Ports

  • Ports declaration
  • Data types
  • Physical
  • Abstract
  • Constant

Topic 4: Operators

  • Arithmetic Operator
  • Bit Wise
  • Logical
  • Reduction
  • Shift
  • Relational/Equality/Concatenation/Replication/Conditional

Topic 5: Modeling

  • Data Flow
  • Behavioral
  • Structural

Topic 6: Timing Control

  • Inertia Delay
  • Transport Delay
  • Event Control
  • Back-Annotation

Topic 7 : Conditional statement

  • if
  • Nested if
  • Case, casex, casez

Topic 8: User Define Primitives.

  • Process statement / Sensitivity List

Topic 9: Lab Exercise

  • Combinational Logic

Day 2

Topic 10: State Machine

  • Mealy 
  • Moore

Topic 11: Simulation

  • Steps of simulation / Simulation Deltas
  • Test bench


Topic 13: Lab Activities

  • Design Entry
  • Writing Verilog code 
  • Test bench 
  • Simulating Verilog code with Vivado (Xilinx)
  • Synthesize the code

Course Info

Prerequisite

The following knowledge is asummed:

  • Basic electronics

Software Requirement

Pls download and install the following software prior to the class

HRDF Funding

Please refer to this video https://youtu.be/Kzpd-V1F9Xs

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Second, Click Application

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The application status will be updated via the employer’s dashboard, email, and the e-TRiS inbox.

Job Roles

  • Digital IC designers
  • VHDL/VERILOG programmers
  • FPGA architects
  • Embedded design Engineers

Trainers

Dr. Florence Choong: Dr. Florence Choong received the BEng. (First class) from Multimedia University, Malaysia in 2002. She then completed her Masters of Engineering Science (MEngSc) degree in Multimedia University, Cyberjaya in 2005 and PhD in Engineering in 2012. Recently, she has completed her Masters in Business Administration (MBA) from the University of Derby, UK.

Upon graduation, she started her career in the telecommunications and networking industry where she served TM for three years in various departments such as networking, IT, quality assurance and customer service. Being passionate in research and training and educating the youth, she then moved to the academic and research line where she joined Multimedia University (MMU) as a lecturer in 2005. She then moved on to University Tunku Abdul Rahman (UTAR) in 2008 as a senior lecturer. She was the Head of the Electrical and Electronics Engineering department in Taylor’s University leading the programme to its first accreditation. At present, she is senior lecturer and is also very active in research. She has a total of more than 10 years of teaching experience. She is also a Chartered Engineer and is registered with the Board of Engineers Malaysia (BEM) and IEM. She is also the advisor to the Taylors IET On Campus.

She is author and co-author of numerous international journal and conference papers published by renowned journals in power quality, VLSI system design and artificial intelligence. Her current research interests are in the area of artificial intelligence, digital and VLSI design. She has also extended her skills and knowledge in this area through various consultancy works.

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