Course Information

  • Sessions 2 days
  • Duration 15 hrs
  • Level Intermediate
  • Assessment NA

Venue

Kuala Lumpur: G-3A-02, Suite Pejabat Korporat, KL Gateway, No 2, Jalan kerinchi, Gerbang kernichi Lestari, 59200 Kuala Lumpur, Malaysia
Penang: Jalan Sungai Dua, 11700 Penang, Malaysia.

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Certification

  • Certificate of Completion from Tertiary Courses - Upon meeting at least 75% attendance and passing the assessment(s), participants will receive a Certificate of Completion from Tertiary Courses.

FPGA Designer Training

Course Code: C421
  • HRDF

What's This Course About

Embark on a transformative journey with FPGA Designer Training, meticulously tailored for those passionate about FPGA design and optimization. Dive deep into the intricate workings of both ALTERA and Xilinx FPGA architectures, garnering a robust understanding that sets the foundation for successful FPGA projects. Our course walks you through the detailed nuances of the tool flows of these leading FPGA technologies, ensuring a seamless design experience.

Venture beyond just architectural insights, embracing the art of writing synthesizable codes, which is the cornerstone of any FPGA project. Harness the power of in-built libraries, understanding their intricate functionalities, and leverage them for efficient FPGA designs. Additionally, the training accentuates the crucial stages of downloading code into FPGA and offers hands-on experience on its debugging features. By the end of this course, be well-equipped with the expertise to tackle any FPGA challenge, ensuring optimal designs and smooth project executions.

WSQ Funding

Full Fee 1,800.00 Before GST
GST 162.00 9% of fee
Baseline Nett 1,062.00 SG/PR age 21+ · 50% funded
MCES / SME Nett 702.00 SG age 40+ · 70% funded
Funding and Grant Applications

No funding is available for this course

Course Fee

MYR1,800.00

Additional Note

Please bring your own laptop for hands-on training. If you don't have laptop, we can provide spare laptop for training use.

Disclaimer: The course dates displayed on our website are tentative and subject to trainer availability. We will confirm the final date after checking with the trainer. You are also welcome to email us your preferred date at sales@tertiarycourses.com.my, and we will do our best to coordinate with the trainer's schedule.

Post-Course Support

  • We may provide consultation related to the subject matter after the course.
  • Please email your queries to sales@tertiarycourses.com.my and we will forward your queries to the subject matter experts and get back to you as soon as possible.

Cancellation & Reschedule Policy

  • We reserve the right to cancel or re-schedule the course due to unforeseen circumstances. If the course is cancelled, we will refund 100% to participants.
  • Note: the venue of the training is subject to changes due to class size and availability of the classroom. The minimum class size to start a class is 3 Pax.

Course Details

Course Details

What You'll Learn

Topic 1: Introduction to FPGA

Cyclone/Stratix device Architecture

Introduction to Quartus II

Creating Project

Using Editor & Design Entry

Topic 2: Analysis and Elaboration

I/O Assignment

Configure voltage for I/0

I/O Assignment Analysis

Synthesis

Netlist Viewer

Topic 3: Constraints

Importance of Constraints in Design

Clock frequency

Asynchronous & Synchronous Design

False Path/Multicycle path

Topic 4: Debugging Tools

Power Analysis

SignalTap II embedded logic analyzer

JTAG Chain Debug Tool

In-System Memory Content Editor

Topic 5: Placing Design in FPGA

Fitter (Place & Route)

Chip Planner

Assembler (Generating Programming file)

Downloading Design in FPGA

Topic 6: Static Time analysis (STA)

Running TimeQuest Timing Analyzer

Understanding reports

Understand setup/hold violation & failing paths

Constraining and understanding TCL Commands

Course Info

Promotion Code

Your will get 10% discount voucher for 2nd course onwards if you write us a Google review.

Minimum Entry Requirement

Knowledge and Skills

  • Able to operate using computer functions
  • Minimum 3 GCE ‘O’ Levels Passes including English or WPL Level 5 (Average of Reading, Listening, Speaking & Writing Scores)

Attitude

  • Positive Learning Attitude
  • Enthusiastic Learner

Experience

  • Minimum of 1 year of working experience.

Target Age Group: 18-65 years old

Minimum Software/Hardware Requirement

Software:

TBD

Hardware: Window or Mac Laptops

Job Roles

Job Roles

  • Digital IC Aesigners
  • VHDL/VERILOG Arogrammers
  • FPGA Architects
  • Embedded design Engineers

Trainers

Trainers

Saeid is co-founder of Skymics Sdn Bhd. He has 8 years of experience in the field of IoT (Internet of Things) and Information Technology. He is a certified IBM IoT Practitioner and instructor, and a Certified Citizen Data Scientist Train-The-Trainer. He has been co-inventor of 3 inventions during the last 4 years.

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